ADS8328 Dual ADC: 7 Checks for TAG Bits and Conversion Identity
ADS8328 Dual ADC: 7 Checks for TAG Bits and Conversion Identity
Plan ADS8328 acquisition with seven checks for dual-rail logic, configuration defaults, channel TAG bits, conversion timing and old-versus-new results. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Separate analog limits from digital-interface supply
ADS8328 combines a sixteen-bit SAR converter with a two-channel input multiplexer. Its analog supply operates from 2.7 V to 5.5 V, while the digital-interface supply has its own documented limits. Review both domains and every host input/output threshold before connecting the bus. The analog range is unipolar relative to the common input, not a general-purpose bipolar differential range. Use protected low-voltage sources for initial tests and keep reference and input nodes within the recommended operating conditions. Manufacturer documentation.
2. Read configuration rather than assuming a simple SPI ADC
The device has a command register and a twelve-bit configuration register. Power-on defaults include automatic channel selection, internal conversion clock, manual conversion triggering and enabled TAG output on ADS8328. These choices differ from a bare converter that merely emits sixteen bits whenever chip select falls. Read back configuration after reset and after each intentional mode change. Include register values in diagnostic logs so a reset or unexpected command cannot silently alter sample sequencing halfway through an experiment. Manufacturer documentation.
3. Know when transmitted ones restore default settings
A configuration write uses the four-bit 1110 command followed by twelve configuration bits. The 1111 command restores the default configuration, and tying the serial input high can issue that command whenever at least four clocks are sent. That convenience is dangerous when a custom configuration is intended. Make the command stream deliberate and inspect it with a logic analyzer. Treat the receive and transmit sides of the same serial transaction as independent responsibilities; reading data also sends command bits. Manufacturer documentation.
4. Use TAG to preserve channel identity across cycles
In automatic channel mode, the dual converter samples the channels in sequence, beginning with channel zero in the cycle identified by the configuration rules. The optional TAG bit follows the sixteen conversion bits and identifies channel zero or one. Since TAG is enabled by default on ADS8328, an ordinary sixteen-clock receive discards useful identity information. Allocate and decode the complete required transfer, preserve channel identity with each sample, and test with two clearly different constant input levels before trusting alternating data. Manufacturer documentation.
Newest in the store
5. Trigger conversion separately from the read transaction
For manual triggering, a falling CONVST edge starts conversion independently of FS/CS. The minimum low pulse is 40 nanoseconds, and completion depends on the selected conversion clock. If serial clock supplies the conversion clock, the device uses SCLK divided by two, introducing additional timing and synchronization requirements. Do not replace these rules with a generic delay copied from another ADC. Use the configured EOC/INT function and the manufacturer timing diagrams to establish when the conversion has actually completed. Manufacturer documentation.
6. Distinguish a previous result from the newest one
Conversion data reach the output register at the next falling FS/CS edge. A read selected before conversion completes returns the previous result; a correctly timed later selection returns the new one. The datasheet cautions against placing chip select precisely at conversion completion and defines a quiet zone around sampling. Respect the documented conversion-clock separation and avoid serial transitions in that quiet interval. A plausible numeric value is not evidence that the host read the conversion it intended to associate with a timestamp. Manufacturer documentation.
7. Verify framing, channel order and scaling together
The data are straight binary, with an ideal step of VREF divided by 65536; midscale is 0x8000, not signed zero. Initial post-reset serial data can be all ones and should not be accepted as a qualified analog result. Log raw frames, TAG, configuration, trigger and completion times, then compare both input channels against known voltages. Exercise reset and a channel-mode change to confirm the pipeline restarts coherently. Report aggregate conversion throughput separately from the effective sample rate of each channel. Manufacturer documentation.
Related reading: ADS8332 Multiplexed ADC: 7 Checks for Acquisition and Channel Tags.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.