PCM1861 Audio ADC: 7 Checks for Hardware Straps and Clocks
PCM1861 Audio ADC: 7 Checks for Hardware Straps and Clocks
Bring up a PCM1861 audio ADC with seven checks for hardware-mode straps, analog routing, fixed gain, serial format, clock ownership and qualified samples. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Identify the hardware-controlled family member
PCM1861 is the hardware-controlled, two-channel member with the higher SNR grade in its pair. It is not the software-controlled PCM1863, despite sharing a family datasheet. Do not expect an I2C scan or register-write sequence to configure its gain and routing. Start from the PCM1860 and PCM1861 pin table and review MD0 through MD6. Save the full part code and board schematic so later firmware work does not accidentally target another family architecture. Manufacturer documentation.
2. Review supply and reference connections by pin
The family is designed around a single 3.3 V supply arrangement, with internal supply circuitry and specified options for individual domains. Follow the exact recommended connections and decoupling for AVDD, DVDD, IOVDD, LDO and VREF rather than treating every power-looking pin as an interchangeable input. VREF is a reference decoupling point, not a general external power rail. Match the digital interface voltage to the host and prevent unintended back-powering through clock or data connections during startup. Manufacturer documentation.
3. Document the analog route and fixed PGA gain
The hardware-controlled device provides defined analog selection and fixed gain choices rather than the fully programmable routing and gain behavior of software-controlled relatives. Select the applicable MD settings from the pin tables and document which physical input reaches each output channel. Check single-ended versus differential wiring and permitted input amplitude at the selected gain. A higher gain reduces the external signal required to reach full scale; an unclipped line-level input at one setting may overload another. Manufacturer documentation.
4. Specify every mode strap and audio format
Create a complete mode-strap table for the board, including clock roles, input selection, gain and serial output format. Use the documented pin levels and resistor arrangements where required; do not leave a pin undefined because a neighboring schematic happened to work. The hardware-controlled output formats include I2S and left justified, not every format offered by software-controlled family members. Align the host receiver with the selected format, word handling and channel order before interpreting an apparently active data stream. Manufacturer documentation.
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5. Give the audio clocks a single owner
Master and slave settings determine which device drives BCK and LRCK. Avoid connecting two clock outputs together. For the documented hardware-controlled clock arrangements, review MD0 and MD1 and the allowed master-clock ratios; the interface uses sixty-four bit clocks per stereo frame in the stated master and slave configurations. Evaluate SCKI or crystal-based arrangements from the appropriate section instead of assuming an arbitrary clock is auto-detected. Measure clock frequencies and their relationship at the actual device pins. Manufacturer documentation.
6. Separate energy detection from complete audio readiness
The hardware-controlled device has fixed-threshold energy detection, but it does not inherit the full programmable interrupt and signal-loss feature set of the software-controlled members. A detection indication is therefore not a substitute for valid clocks, correct routing or unclipped samples. Define startup and low-power behavior using the hardware-device documentation and host capture policy. Discard unqualified startup samples and avoid calling silence a wiring fault until the selected input, gain and operating state have been checked. Manufacturer documentation.
7. Validate channel identity before judging audio quality
Begin with a known low-level signal on one selected input and a quiet counterpart, then swap them to verify channel order and routing. Record mode straps, input amplitude, gain, sample rate and all clock frequencies with the captured data. Check clipping and DC behavior before measuring noise or distortion. Datasheet SNR is a specified test result under defined conditions, not a guaranteed board measurement. Preserve the capture format and analysis bandwidth so subsequent hardware or clock changes can be compared meaningfully. Manufacturer documentation.
Related reading: PCM1863 Audio ADC: 7 Checks for Channel Routing and Clock Identity.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.