ADS131M04 ADC: 7 Checks for Six-Word Frames and FIFO Recovery
ADS131M04 ADC: 7 Checks for Six-Word Frames and FIFO Recovery
Plan ADS131M04 acquisition with valid PGA ranges, six-word framing, CRC write caveats, FIFO recovery and synchronized channel records. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Define four channels and the complete analog envelope
ADS131M04 is a four-channel simultaneous-sampling, twenty-four-bit delta-sigma converter with programmable gain. Its analog and digital supplies operate from 2.7 V to 3.6 V under documented conditions. Check individual input-pin limits as well as the differential range, which depends on reference voltage and PGA gain. The integrated negative charge pump permits specifically bounded below-ground inputs, not arbitrary negative voltages. Simultaneous conversion does not automatically remove sensor delays or front-end phase mismatch. Manufacturer documentation.
2. Match PGA gain and filtering to the signal
The PGA supports gains up to 128, but increasing gain reduces the allowed differential signal range and changes input characteristics. Compare source impedance, noise and worst-case amplitude at the selected setting. Choose data rate and oversampling from the intended signal bandwidth, then allow the documented digital-filter settling after changes. A twenty-four-bit result is not a guarantee of twenty-four useful bits. Treat phase calibration and offset or gain calibration as explicit configurations with retained parameters, not automatic evidence of accuracy. Manufacturer documentation.
3. Parse the normal six-word SPI frame
For most commands, the output frame contains a response to the previous frame’s command, four channel-data words and an output CRC word. Word length can be sixteen, twenty-four or thirty-two bits according to configuration. Build the parser from that exact layout, including sign representation and any padding. Some register transactions extend the frame, so do not assume every command has the normal length. Verify command-response latency before associating an acknowledgement with the configuration just sent. Manufacturer documentation.
4. Implement the correct CRC and the WREG exception
The output CRC always appears; the host may ignore it but cannot disable its generation. Input CRC is configurable. The documented calculation uses a FFFF hexadecimal seed and the selected CCITT or ANSI polynomial. Crucially, WREG executes even when its input CRC fails, unlike other commands subject to the integrity check. Read the configuration back and retain CRC_ERR events. A failed input check must not be interpreted as proof that no register changed or that the preceding acquisition setup remains intact. Manufacturer documentation.
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5. Recover the two-deep FIFO after a reading pause
The output mechanism can retain two samples per channel. After missed reads or an acquisition pause, both FIFO positions may be occupied and DRDY behavior can be misleading if the host expects normal consecutive sampling. The manufacturer describes either resynchronizing to clear the FIFOs or reading two packets promptly when collection resumes. Apply the chosen method deliberately and mark any resulting gap in the record. Timestamping a retrieved packet does not prove it was the newest conversion. Manufacturer documentation.
6. Distinguish synchronization from a full reset
SYNC/RESET is an active-low dual-function pin whose pulse duration determines whether the operation synchronizes conversions or resets the device. Use the specified clock-cycle timing rather than a vague software delay. A reset also requires the documented recovery interval and configuration checks before communication and valid acquisition resume. Register-map CRC is a separate integrity mechanism that can flag intentional writes as well as unintended changes. Record the cause before clearing status or accepting new data. Manufacturer documentation.
7. Validate raw frames and channel identity with known inputs
Apply independent bounded test signals to all four inputs and verify order, sign, scale and settled response at the intended rate. Inspect raw SPI traffic and preserve CRC failures, overruns, synchronization events and invalid intervals. Check the selected phase-calibration settings against the actual signal chain. Save clock, gain, filtering, reference and parser configuration with the dataset. This creates traceable simultaneous records without claiming isolated measurement, automatic mains safety or independent bench accuracy from the nominal resolution alone. Manufacturer documentation.
Related reading: ADS131A02 Dual ADC: 7 Checks for Four-Word Frames and Integrity.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.