ADS7128 ADC: 7 Checks for CRC Recovery and Honest RMS Results
ADS7128 ADC: 7 Checks for CRC Recovery and Honest RMS Results
ADS7128 checks for byte-wise CRC, error recovery, AVDD scaling, channel identity and RMS window and DC-subtraction limits. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Establish reference and input conditions first
The ADS7128 is an eight-channel twelve-bit multiplexed ADC with configurable GPIOs, CRC support and digital processing functions. AVDD operates from 2.35 V to 5.5 V, DVDD from 1.65 V to 5.5 V, and the analog supply is the conversion reference. Ordinary straight-binary code scaling therefore depends on AVDD divided by 4096. Provide the recommended decoupling and a bounded analog source. The presence of RMS or zero-crossing features does not make the input suitable for direct connection to mains or other hazardous signals. Manufacturer documentation.
2. Keep channel configuration and acquisition explicit
Each multifunction terminal can be configured as an analog input or GPIO. Pin mode, GPIO direction and drive type have separate controls and should be read back after initialization. The ADC path is multiplexed rather than eight simultaneous samplers, so source impedance and acquisition settling affect results. Preserve channel identity through selection and readout, including any appended format. A valid CRC confirms transferred bits, not that the correct source was selected or that a high-impedance input settled before conversion. Manufacturer documentation.
3. Implement byte-wise CRC rather than a generic checksum
The enabled interface CRC uses CRC-8-CCITT with polynomial x to the eighth plus x squared plus x plus one. The documented interface appends CRC information per transferred data byte; do not replace that framing with one checksum assumed to cover an entire arbitrary application packet. Follow the exact manufacturer timing and coverage rules for reads and writes and test against known transactions. Configure host framing and device CRC state together, since disagreement about CRC enable changes how traffic must be interpreted. Manufacturer documentation.
4. Treat CRC errors as a recovery state
When an incoming CRC error is detected, erroneous data is ignored and CRC_ERR_IN is set. Further register writes are disabled until that error is cleared by writing one to the documented flag. Error notification can also be mapped to the alert mechanism or appended status. A blind retry loop that never checks the flag can therefore leave intended configuration unapplied. Verify state after recovery and consider the autonomous conversion-on-error setting explicitly rather than assuming every conversion always stops or always continues after an interface error. Manufacturer documentation.
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5. Define what the RMS result includes
The RMS module operates on a selected analog channel over a programmed sample block and returns a sixteen-bit result. Its documented scale is AVDD divided by 65536 per result step; that output format does not guarantee sixteen-bit absolute analog accuracy. Decide whether the application needs total RMS or the supported DC-subtracted behavior before interpreting the number. The analog signal remains unipolar at the ADC input, so any external bias, attenuation and protection must be designed and reviewed independently. Manufacturer documentation.
6. Respect DC subtraction and computation completion
When DC subtraction is enabled, the datasheet requires the DC input level within its specified tolerance around half AVDD. This is not an unrestricted offset-removal operation for every biased waveform. Configure the RMS channel and sample count, start computation, and allow the documented additional forty channel samples needed to complete it. Poll RMS_DONE or use the mapped alert before accepting the result. Trigger the documented new-measurement sequence for another block instead of repeatedly reading a stale register pair as fresh data. Manufacturer documentation.
7. Validate integrity and measurement meaning separately
Record supply-reference voltage, selected channel, source waveform, sampling configuration, CRC state, RMS window, completion indication and result scaling. Test communication recovery with a controlled software fixture rather than injecting unsafe electrical disturbances. Compare RMS results with a suitable reference over known low-voltage waveforms and valid bias conditions. Keep averaging, RMS computation and zero-crossing detection as distinct functions. A clean checksum and a sixteen-bit register are useful evidence, but neither proves analog accuracy, freshness or application-level electrical safety on its own. Manufacturer documentation.
Related reading: TLA2528 ADC: 7 Checks for Channel Identity and Averaged Data.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.