TCA9537 GPIO Expander: 7 Checks for Reset and Lost Interrupts
TCA9537 GPIO Expander: 7 Checks for Reset and Lost Interrupts
Plan TCA9537 GPIO control with seven checks for the fixed I2C address, safe output setup, reset defaults, input reads and interrupt race conditions. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Confirm the four-port device and fixed address
TCA9537 provides four GPIOs, an active-low reset input and an open-drain interrupt output. Its fixed seven-bit I2C address is 0x49. Do not borrow the address or special registers of another four-port expander. Most microcontroller APIs expect the seven-bit value, not an already shifted address byte. Check the package pinout, supply and fitted board connections before scanning the bus; a successful acknowledge identifies a responding address, not necessarily a correctly configured load. Manufacturer documentation.
2. Design the bus and external signals for the selected rail
The operating supply range is 1.65 V to 5.5 V. Select SDA and SCL pull-ups for bus capacitance, speed and the voltage tolerance of every connected device, rather than treating a resistor value as universal. INT needs a pull-up, and an unused RESET input needs the specified pull-up to VCC. Provide defined bias for external switches and sensors. Review port input tolerance separately from output operation; an output driven against another source can create damaging contention. Manufacturer documentation.
3. Program the output latch before changing direction
The register map is compact: input at 0x00, output at 0x01, polarity inversion at 0x02 and configuration at 0x03. Configuration bits default to ones, leaving ports as inputs; output latch bits default high. To enable a load with an active-low control, first write its inactive latch value while the port remains an input, then change that direction bit. Preserve the other ports with a reviewed software shadow so one update does not accidentally enable an unrelated circuit. Manufacturer documentation.
4. Read pins rather than mistaking latch state for feedback
Reading the output register returns stored output selection, not a measurement of the physical pin. The input register reflects port levels and is the place to inspect actual logic state, including an output when appropriate. Only the low four bits correspond to real ports; upper input bits read as ones. Keep input polarity inversion separate from output drive and avoid carrying an eight-port mask into a four-port state machine. Use a voltmeter or logic analyzer to confirm the resulting behavior. Manufacturer documentation.
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5. Treat INT as a change indication, not an event counter
An input edge can assert INT, and reading the relevant input port resets the interrupt circuit. The datasheet warns that changes during the acknowledging clock can be lost or produce very short interrupt pulses. A pin returning to its original level can also remove the indication. This makes INT unsuitable as a guaranteed edge counter or timestamp source. Use direct hardware capture for pulse counting, and apply deliberate debounce and periodic input reconciliation for ordinary switches. Manufacturer documentation.
6. Reconcile state after every interrupt and reset
A robust handler schedules an input read, compares the returned port state with the software snapshot, handles the application change and checks whether service is still required. Reading an output or configuration register is not a substitute for reading the input port. Changing a pin from output to input can itself generate an interrupt. RESET restores register defaults and the bus state machine, so reset recovery must also rebuild direction, polarity, latch and host expectations before enabling dependent functions. Manufacturer documentation.
7. Test races without attaching hazardous loads
Begin with indicator LEDs or logic-level dummy loads and capture RESET, SCL, SDA, INT and the affected port. Test an edge during a read, a bounce sequence, direction changes and a reset while the host remains powered. Include bus error paths and a bounded retry policy, but do not assume a missing interrupt means the port did not change. Document the final stable input state and the limitations on event capture rather than claiming every transition was recorded. Manufacturer documentation.
Related reading: TCA9536 GPIO Expander: 7 Checks for P3 Interrupt and Soft Reset.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.