PCM1807 Audio ADC: 7 Checks for SPI Control and Fade Timing
PCM1807 Audio ADC: 7 Checks for SPI Control and Fade Timing
Configure PCM1807 stereo capture with seven checks for SPI control words, audio clock roles, format selection, reset delay, fade timing and clock-halt recovery. This is a documentation-based planning guide, not a report of independent hands-on testing.
1. Separate the audio data port from the control port
PCM1807 is a stereo audio ADC with a serial audio output and a separate SPI-style control interface. Its MD, MC and MS signals configure registers; they are not interchangeable with DOUT, BCK and LRCK. Start from the fourteen-pin device drawing rather than a strap-controlled relative’s schematic. The analog and digital supplies have different nominal voltages, so check both rail ranges and interface thresholds before expecting communication or a meaningful audio stream. Manufacturer documentation.
2. Review the single-ended analog input network
The documented nominal input span is 3 V peak to peak under specified conditions. Follow the coupling, bias and reference-decoupling guidance for the intended source rather than assuming a bipolar line-level signal can be attached directly. Verify the selected amplitude on each channel and avoid clipping before measuring noise or distortion. The built-in filtering does not remove the need for correct board-level input conditioning. Keep reference and analog return paths away from digital clock currents. Manufacturer documentation.
3. Build the complete sixteen-bit control word
The control word consists of a leading zero, a seven-bit register index and eight data bits. Use the MS, MC and MD timing diagram for a complete write, including the required MS high interval before another transaction. Do not send only a data byte or substitute the twenty-four-bit format used by another converter. Keep the transmitted register image in host diagnostics and verify a representative sequence on a logic analyzer before relying on higher-level audio settings. Manufacturer documentation.
4. Assign audio clock roles through the correct settings
The device supports master and slave audio operation, with supported system-clock ratios of 256, 384 and 512 times the sample rate. In master mode the corresponding configuration is supplied through the serial control port. Check the actual clock and sampling-frequency table, and ensure only one device drives BCK and LRCK. Select I2S or left-justified audio deliberately in both ADC and receiver. Valid control writes and visible serial activity do not prove that channel alignment or audio word interpretation is correct. Manufacturer documentation.
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5. Allow reset delay and signal-dependent fade-in
After the power-on reset interval, the documented initial data delay is 8960 divided by sample rate, followed by fade-in behavior. At 48 kHz, that delay alone is about 187 milliseconds, before the additional fade timing and other startup requirements. Fade processing uses zero-cross detection, so completion can depend on the input frequency and timeout rules. Do not reuse the shorter readiness interval of a similar audio ADC or declare zero output an immediate hardware failure during startup. Manufacturer documentation.
6. Understand mute and clock-halt recovery separately
Mute with fade processing is different from abruptly stopping the system clock. Halting SCKI triggers the documented reset and power-down behavior and forces output to zero; some register state is reset while mode-control state has specific retention behavior. Follow the power-down recommendations before clock halt and the restart sequence afterward. Keep the host capture state aware of fade and reset intervals. A resumed clock does not imply the next received frame already represents fully settled input audio. Manufacturer documentation.
7. Verify channel identity before judging performance
Capture a known low-level signal on one input at a time, confirming format, channel order, polarity and clipping limits. Exercise mute, power-down and clock restart while marking unqualified frames rather than merging them into continuous valid data. Record control words, rail voltages, clock ratios, sample rate and fade timing with each capture. Typical SNR and twenty-four-bit output width do not establish equivalent board-level resolution. Compare noise and distortion only with defined levels, bandwidth and operating conditions. Manufacturer documentation.
Related reading: PCM1803A Audio ADC: 7 Checks for Oversampling and Startup Data.
Catalog note: The exact-part search did not return a matching Epro listing during preparation. Check the current catalog; this guide makes no price, availability or included-accessory claim.