TCA9545A I2C Switch: 7 Checks for Channel Masks and Interrupts
Plan a TCA9545A bus tree with STOP-latched channel masks, address-conflict control, downstream pull-ups, interrupt routing and hardware reset recovery.
Electronic Pro Blog | Epro
PCM1804 Audio ADC: 7 Checks for Differential Inputs and DSD
Review PCM1804 analog bias, differential drive, PCM or DSD pin roles, sample-rate clocks and reference settling before capturing a stereo audio stream.
OPA197 ADC Driver: 7 Checks for Multiplexer Recovery and Settling
Plan an OPA197 multiplexed front end with differential-input protection behavior, full-step settling, ADC kickback control and load-dependent output headroom.
INA190 Current Monitor: 7 Checks for Package-Specific Enable
Plan INA190 low-current measurement with the correct package enable capability, REF scaling, shunt leakage budget and settling after wake or overload.
TPS22917 Load Switch: 7 Checks for Reverse Blocking and Timing
Review TPS22917 switching with threshold-based reverse-current blocking, CT rise control, QOD discharge and the correct active-high or active-low variant.
TPS62177 Buck Supply: 7 Checks for Sleep Mode and Wake Load
Plan a TPS62177 fixed 3.3 V rail with correct SLEEP polarity, wake-load timing, power-good behavior, component selection and shutdown expectations.
TMP103 Sensor Network: 7 Checks for Multiple-Device Reads
Plan TMP103 temperature networks with fixed-address variants, signed eight-bit values, multiple-device read ordering and dummy slots for missing variants.
DRV8835 Dual Driver: 7 Checks for Modes and Logic-Supply Sleep
Plan DRV8835 dual-motor control with the correct interface mode, braking truth table, separate supplies and actual VCC-based sleep behavior.
DAC8560 Voltage DAC: 7 Checks for Internal Reference Commands
Review DAC8560 output generation with its default internal reference, external-reference handover, special clock requirements, feedback and startup behavior.
ADS8332 Multiplexed ADC: 7 Checks for Acquisition and Channel Tags
Plan ADS8332 acquisition with the exposed mux-to-ADC path, conversion triggering, reference drive and channel identification matched to the selected mode.